In a manufacturing process of a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), various kinds of operation tests are performed in a wafer state in many cases. In the operation test, a defective address at which data reading or data writing cannot be performed is detected. A detected defective address is saved by a redundant cell. The defective cell is replaced by the redundant cell mainly by the trimming of a fuse.
The operation test in the wafer state is not performed for each chip, and is generally performed for plural chips in parallel. In other words, by commonly connecting a clock terminal, an address terminal, and a command terminal among plural chips to be tested, a common clock signal, a common address signal, and a common command are given to these chips. In this state, data are actually read and written. Because at least the output data needs to be individually handled for each chip, it should be understood that data input and output terminals are not connected in common.
However, at this state of the operation test, fine adjustment of a reference voltage generated inside the chip is not completed, and a correct test cannot be performed in this state. Therefore, conventionally, a reference voltage generated inside the chip is temporarily applied from the outside, and the operation test is performed in this state. A reference voltage applied from the outside is substantially equal to a design value, and the operation test can be performed substantially in the design condition.
However, the reference voltage applied from the outside does not completely coincide with the original reference voltage obtained after the fine adjustment. In other words, even when the reference voltage is fine-adjusted to become close to the design value, the value close to the design value cannot always be obtained for various reasons. Therefore, according to the method of externally applying a reference voltage equal to the design value, the original state of the device after the fine adjustment cannot be correctly realized.
Consequently, according to the conventional method, the operation test is performed in a state of using a reference voltage a little different from the original reference voltage obtained after the fine adjustment. This decreases the accuracy of the operation test. However, a deviation from the reference voltage in the operation test is small, and therefore, the accuracy of the operation test does not decrease substantially. When a voltage reduction and a density increase of the semiconductor memory device further progress, the accuracy of the operation test decreases to an unnegligible degree due to a slight deviation of the reference voltage.
In order to solve the above problems, there might be a method that a reference voltage is fine-adjusted by fuse trimming, and thereafter, an operation test of detecting a defective address is performed. According to this method, however, after detecting a defective address, a cell needs to be replaced again by a redundant cell by fuse trimming. In other words, two trimming processes are necessary. Therefore, manufacturing cost increases, and, moreover, damage applied to the electrode pad increases, resulting in a reduction of reliability.
As another method of solving the above problems, a code for temporarily performing the fine adjustment of a reference voltage is input in the test mode, and an operation test of detecting a defective address is performed in this state. However, the entry to this test mode requires the input of a predetermined code from an address terminal in a state that a mode register set (MRS) command is issued. Therefore, individual codes cannot be input to chips to be tested. It is of course possible to configure such that individual addresses are input to chips to be tested, without connecting an address terminal in common to the chips. In this case, a tester becomes substantially complex.
Techniques described in Japanese Patent Application Laid Open Nos. 2003-307545, 2004-46927, 2004-198367, and 2004-71098 are also known, as other conventional techniques regarding the test of a semiconductor memory device.